11.-12. März 2025, Rostock/Warnemünde
Programm
Dienstag, 11.03.2025 | |
| 8:30 - 9:00 | Registrierung |
| 9:00 - 9:15 | Eröffnung Christian Haubelt, Universität Rostock |
| 9:15 - 9:45 |
Keynote Im Fahrstuhl durch die Gotlandsee Dr. Ralf Prien, Institut für Ostseeforschung, Warnemünde |
| 9:45 | Session 1: TestingModeration: Markus Wedler, Synopsys GmbH |
| 9:45 - 10:00 | Using Computational Stress to Derive Stress Robustness and Timing Behaviors on Hard Real-Time Operating Systems Max Brand1, Albrecht Mayer1 and Frank Slomka2 1Infineon Technologies AG 2Ulm University |
| 10:00 - 10:15 | Towards Semantic Abstraction of Test Programs Matthias Sauppe1, Daniel Manns2 and Ulrich Heinkel1 1TU Chemnitz 2Steinbeis-Forschungszentrum Systementwurf und Test |
| 10:15 - 10:30 | RVVTS: A Modular, Open-Source Framework for Positive and Negative Testing of the RISC-V 'V' Vector Extension (RVV)Übersichtsvortrag Manfred Schlägl and Daniel Große Johannes Kepler University, Linz |
| 10:30 - 10:35 | Demo Pitch: Open-Source Software for Heaviside Real-Time Analysis Iwan Feras Fattohi1, Christian Prehofer2 and Frank Slomka1 1Ulm University 2Technical University of Munich |
| 10:35 - 11:30 | Pause und Postersession |
| 11:30 | Session 2: Virtual Prototyping and SimulationModeration: Matthias Jung, Universität Würzburg |
| 11:30 - 11:45 | Symbolic Execution of Unmodified SystemC Peripherals Übersichtsvortrag Karl Aaron Rudkowski, Sallar Ahmadi-Pour and Rolf Drechsler University of Bremen |
| 11:45 - 12:00 | Minimizing simulation effort during temporal distribution analysis in real-time systems Andre Gaschler and Frank Slomka Ulm University |
| 12:00- 12:15 | Verilator and FireSim RTL Simulations on a HPC Cluster: A Comparative Case Study Kai Arne Hannemann, Hüseyin Berke Bütün, Wolfgang Mueller and Christoph J. Scheytt Paderborn University |
| 12:15 - 12:30 | Towards Non-Intrusive SystemC Checkpointing for Digital Virtual Prototypes Deepak Ravibabu1, Muhammad Hassan1, Thilo Vörtler2, Karsten Einwich2, Rolf Drechsler3 and Daniel Große4 1Cyber-Physical Systems, DFKI GmbH 2COSEDA Technologies GmbH 3University of Bremen 4Johannes Kepler University, Linz |
| 12:30 - 13:30 | Mittagessen |
| 13:30 | Session 3: Architectures and System ModelingModeration: Martin Radetzki, Universität Stuttgart |
| 13:30 - 13:45 | Latency-Constrained Neural Architecture Search for U-Nets on Graphics Processing Units Stefan Groth1, Christian Heidorn1, Moritz Schmid2, Jürgen Teich1 and Frank Hannig1 1Friedrich-Alexander-Universität Erlangen-Nürnberg 2Siemens Healthineers |
| 13:45 - 14:00 | Design Exploration für RISC-V Prozessoren zur Optimierung von Erklärbarkeit für Maschinelles LernenÜbersichtsvortrag Johannes Rust, Rolf Drechsler and Serge Autexier DFKI Bremen |
| 14:00 - 14:15 | Improving Design Generation by Interface Configuration Propagation Natalie Simson, Paritosh Kumar Sinha and Wolfgang Ecker Infineon Technologies AG |
| 14:15 - 14:30 | Exploration of Clock and Power Gating Tradeoffs for the Design of Self-Powering Dataflow Networks Abrarul Karim, Joachim Falk and Jürgen Teich Friedrich-Alexander-Universität Erlangen-Nürnberg |
| 14:30 - 14:45 | Platform-Aware RTL Generation: Bridging the Gap between Design and Implementation Mohamed Badawy1,2, Nicolas Gerlin1, Paritosh Kumar Sinha1, Endri Kaja1, Jad Al Halabi1, Stephanie Ecker1,3, Natalie Simson1,2 and Wolfgang Ecker1,2 1Infineon Technologies AG 2Technical University of Munich 3CHIPGLOBE GmbH |
| 14:45 - 15:45 | Pause und Postersession |
| 15:45 | Session 4: Specification and Code GenerationModeration: Wolfgang Müller, Universität Paderborn |
| 15:45 - 16:00 | Enhancing LLM-Generated Hardware Documentation: Post-Processing and Prompt Engineering Techniques Robert Kunzelmann1,2, Saruni Fernando1,3 and Wolfgang Ecker1 1Infineon Technologies AG 2Technical University of Munich 3Rosenheim Technical University of Applied Sciences |
| 16:00 - 16:15 | Erfassung und Austausch prozessspezifischer Anforderungen entlang der Wertschöpfungskette Franziska Mayer, Christian Schott, Davis John Chellappa, Erik Markert and Ulrich Heinkel Technical University of Chemnitz |
| 16:15 - 16:30 | Rustifying Embedded Software Development: A Model-Based Code Generation Approach for Auto-Generation of C and RUST Raphael Kunz1,2, Mayuri Bhadra1,2, Stephanie Ecker1,2,3 and Wolfgang Ecker1,2 1Infineon Technologies AG 2Technical University of Munich 3CHIPGLOBE GmbH |
| 16:30 - 16-45 | Parameterized Construction and Constraint-Driven Validation of Formal Hardware Specifications for Efficient Code Generation Robert Kunzelmann1,2, Maximilian Berger1,2 and Wolfgang Ecker1 1Infineon Technologies AG 2Technical University of Munich |
| 16:45 - 17:30 | Pause und Postersession |
| 17:30 - 18:00 | Sitzung der Fachgruppen 3 und 4 GMM/ITG/GI Daniel Große, Johannes-Kepler-Universität Linz Wolfgang Müller, Universität Paderborn |
| 19:00 | Abendessen im Restaurant Wenzel Fußgängerroute zum Restaurant (ca. 13 min): https://maps.app.goo.gl/ocTq2izczQrd8Gqy9 |
Mittwoch, 12.03.2025 | |
| 9:00 - 9:45 | Postersession |
| 9:45 | Session 5: Formal Verification and SecurityModeration: Daniel Große, Johannes-Kepler-Universität Linz |
| 9:45 - 10:00 | VeriCHERI: Exhaustive Formal Security Verification of CHERI at the RTLÜbersichtsvortrag Anna Lena Duque Antón1, Johannes Müller1, Philipp Schmitz1, Tobias Jauch1, Alex Wezel1, Lucas Deutschmann1, Mohammad Rahmani Fadiheh2, Dominik Stoffel1 and Wolfgang Kunz1 1RPTU Kaiserslautern-Landau 2Stanford University |
| 10:00 - 10:15 | Hardware Trojan Detection using Formal Verification and AutomationÜbersichtsvortrag Czea Sie Chuah1, Christian Appold2 and Tim Leinmüller2 1Technical University of Munich 2DENSO AUTOMOTIVE Deutschland GmbH |
| 10:15 - 10:30 | Coverage Metrics for Security Property Verification: A Novel Approach Jaimini Nagar1, Thorsten Dworzak1, Sebastian Simon1, Ulrich Heinkel2 and Djones Lettnin1 1Infineon Technologies AG 2Technical University of Chemnitz |
| 10:30 - 10:45 | Embedding Modulo Counter Circuits for their Polynomial Formal VerificationÜbersichtsvortrag Caroline Dominik and Rolf Drechsler University of Bremen, Germany |
| 10:45- 11:45 | Pause und Postersession |
| 11:45 | Session 6: System AnalysisModerator: Frank Slomka, Universität Ulm |
| 11:45 - 12:00 | Data-Driven Probabilistic Evaluation of Logic Properties with PAC-Confidence on Mealy Machines Swantje Plambeck1, Ali Salamati2, Eyke Hüllermeier2 and Goerschwin Fey1 1Hamburg University of Technology 2Ludwig Maximilian University Munich |
| 12:00 - 12:15 | Dead-Code Detection with IC3 using SMT-LIBv2 Solvers Lukas Mentel1, Tobias Seufert2, Karsten Scheibler1 and Christoph Scholl2 1BTC Embedded Systems AG 2University of Freiburg |
| 12:15 - 12:30 | Efficient Hierarchical Decomposition of Repetitive Traces for ML-Driven Analysis Johannes Knödtel and Marc Reichenbach University of Rostock |
| 12:30 - 12:45 | Information Flow Analysis - Understanding the Trade-Offs between Static and Dynamic AnalysisÜbersichtsvortrag Lutz Schammer, Gianluca Martino and Goerschwin Fey Hamburg University of Technology |
| 12:45 - 13:00 | Abschluss |
| 13:00 - 14:00 | Mittagessen |
14:00 Uhr: Ende MBMV 2025
15:00 Uhr: Kooperationstreffen der ZuSE-Projekte
